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Dual 64-and 256-Position I2C Nonvolatile Memory Digital Potentiometers AD5251/AD5252
FEATURES
AD5251: Dual 64-position resolution AD5252: Dual 256-position resolution 1 k, 10 k, 50 k, 100 k Nonvolatile memory1 stores wiper setting w/write protection Power-on refreshed with EEMEM settings in 300 s typ EEMEM rewrite time = 540 s typ Resistance tolerance stored in nonvolatile memory 12 extra bytes in EEMEM for user-defined information I2C compatible serial interface Direct read/write access of RDAC2 and EEMEM registers Predefined linear increment/decrement commands Predefined 6 dB step change commands Synchronous or aysynchronous dual channel update Wiper setting read back 4 MHz bandwidth--1 k version Single supply 2.7 V to 5.5 V Dual supply 2.25 V to 2.75 V 2 slave address decoding bits allow operation of 4 devices 100-year typical data retention TA = 55C Operating temperature -40C to +85C White LED brightness adjustment RF base station power amp bias control Programmable gain and offset control Programmable voltage-to-current conversion Programmable power supply Sensor calibrations
FUNDAMENTAL BLOCK DIAGRAM
VDD VSS DGND WP SCL SDA DATA I2C SERIAL INTERFACE RDAC3 REGISTER COMMAND DECODE LOGIC ADDRESS DECODE LOGIC CONTROL LOGIC RDAC3 A3 W3 B3 RDAC EEMEM EEMEM POWER-ON REFRESH RAB TOL RDAC1 REGISTER RDAC1 A1 W1 B1
CONTROL
AD0 AD1
Figure 1.
APPLICATIONS
Mechanical potentiometer replacement General purpose DAC replacement LCD panel VCOM adjustment
1 2
The terms nonvolatile memory and EEMEM are used interchangeably. The terms digital potentiometer and RDAC are used interchangeably.
GENERAL DESCRIPTION
The AD5251/AD5252 are dual-channel, I2C, nonvolatile memory, digitally controlled potentiometers with 64/256 positions, respectively. These devices perform the same electronic adjustment functions as mechanical potentiometers, trimmers, and variable resistors. The parts' versatile programmability allows multiple modes of operation, including read/write access in the RDAC and EEMEM registers, increment/decrement of resistance, resistance changes in 6 dB scales, wiper setting readback, and extra EEMEM for storing user-defined information such as memory data for other components, look-up table, or system identification information. The AD5251/AD5252 allow the host I2C controllers to write any of the 64- or 256-step wiper settings in the RDAC registers and store them in the EEMEM. Once the settings are stored,
they are restored automatically to the RDAC registers at system power-on; the settings can also be restored dynamically. The AD5251/AD5252 provide additional increment, decrement, +6 dB step change, and -6 dB step change in synchronous or asynchronous channel update modes. The increment and decrement functions allow stepwise linear adjustments, while 6 dB step changes are equivalent to doubling or halving the RDAC wiper setting. These functions are useful for steep-slope nonlinear adjustments such as white LED brightness and audio volume control. The parts have a patented resistance tolerance storing function which enable the user to access the EEMEM and obtain the absolute end-to-end resistance values of the RDACs for precision applications. The AD5251/AD5252 are available in TSSOP-14 packages in 1 k, 10 k, 50 k, and 100 k options and all parts can operate over the -40C to +85C extended industrial temperature range.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 (c) 2004 Analog Devices, Inc. All rights reserved.
03823-0-001
POWERON RESET
AD5251/ AD5252
AD5251/AD5252 TABLE OF CONTENTS
Electrical Characteristics ................................................................. 3 Interface Timing Characteristics................................................ 7 Absolute Maximum Ratings............................................................ 8 ESD Caution.................................................................................. 8 Pin Configuration and Function Description .............................. 9 I2C Interface Timing Diagram.................................................... 9 I2C Interface General Description................................................ 10 I2C Interface Detail Description ................................................... 11 RDAC/EEMEM Write ............................................................... 11 I2C Compatible 2-Wire Serial Bus................................................ 15 Typical Performance Characteristics ........................................... 16 Operational Overview.................................................................... 20 Linear Increment and Decrement Commands ...................... 20 6 dB Adjustments (Doubling/Halving WIPER Setting) ..... 20 Digital Input/Output Configuration........................................ 21 Multiple Devices on One Bus ................................................... 21 Terminal Voltage Operation Range ......................................... 21 Power-Up and Power-Down Sequences.................................. 21 Layout and Power Supply Biasing ............................................ 22 Digital Potentiometer Operation ............................................. 22 Programmable Rheostat Operation......................................... 22 Programmable Potentiometer Operation ............................... 23 Applications..................................................................................... 24 LCD Panel Vcom Adjustment ..................................................... 24 Current-Sensing Amplifier ....................................................... 24 Adjustable High Power LED Driver ........................................ 24 Outline Dimensions ....................................................................... 25 Ordering Guide .......................................................................... 25
REVISION HISTORY
6/04--Revision 0: Initial Version
Rev.0 | Page 2 of 28
AD5251/AD5252 ELECTRICAL CHARACTERISTICS
1 k Version. VDD = 3 V 10% or 5 V 10%; VSS = 0 V or VDD/VSS = 2.5 V 10%; VA = +VDD, VB = 0 V, -40C < TA < +85C, unless otherwise noted. Table 1.
Parameter DC CHARACTERISTICS RHEOSTAT MODE Resolution Resistor Differential Nonlinearity2 Symbol Conditions Min Typ1 Max Unit
N R-DNL
AD5251/AD5252 RWB, RWA = NC, VDD = 5.5 V, AD5251 RWB, RWA = NC, VDD = 5.5 V, AD5252 RWB, RWA = NC, VDD = 2.7 V, AD5251 RWB, RWA = NC, VDD = 2.7 V, AD5252 RWB, RWA = NC, VDD = 5.5 V, AD5251 RWB, RWA = NC, VDD = 5.5 V, AD5252 RWB, RWA = NC, VDD = 2.7 V, AD5251 RWB, RWA = NC, VDD = 2.7 V, AD5252 TA = 25C
-0.5 -1 -0.75 -1.5 -0.5 -2 -1 -2 -30
0.2 0.25 0.3 0.3 0.2 0.5 +2.5 +9
6/8 +0.5 +1 +0.75 +1.5 +0.5 +2 +4 +14 +30
Bits LSB LSB LSB LSB LSB LSB LSB LSB % ppm/C %
Resistor Nonlinearity2
R-INL
Nominal Resistor Tolerance Resistance Temperature Coefficent Wiper Resistance Channel Resistance Matching DC CHARACTERISTIC POTENTIOMETER DIVIDER MODE Differential Nonlinearity3 Integral Nonlinearity3 Voltage Divider Temperature Coefficent Full-Scale Error
RAB/RAB (RAB/RAB) x 106/T RW RAB1/RAB3
IW = 1 V/R, VDD = 5 V IW = 1 V/R, VDD = 3 V
650 75 200 0.15
130 300
DNL INL
AD5251 AD5252 AD5251 AD5252 Code = half scale Code = full scale, VDD = 5.5 V, AD5251 Code = full scale, VDD = 5.5 V, AD5252 Code = full scale, VDD = 2.7 V, AD5251 Code = full scale, VDD = 2.7 V, AD5252 Code = zero scale, VDD = 5.5 V, AD5251 Code = zero scale, VDD = 5.5 V, AD5252 Code = zero scale, VDD = 2.7 V, AD5251 Code = zero scale, VDD = 2.7 V, AD5252
-0.5 -1 -0.5 -2
0.1 0.25 0.2 0.5 25 -3 -11 -4 -16 3 11 4 15
+0.5 +1 +0.5 +2
LSB LSB LSB LSB ppm/C LSB LSB LSB LSB LSB LSB LSB LSB V pF pF
(VW/VW) x 106/T VWFSE
Zero-Scale Error
VWZSE
-5 -16 -6 -23 0 0 0 0 VSS
0 0 0 0 5 16 6 20 VDD
RESISTOR TERMINALS Voltage Range4 Capacitance5 Ax, Bx Capacitance5 Wx Common-Mode Leakage Current DIGITAL INPUTS and OUTPUTS Input Logic High Input Logic Low Output Logic High (SDA) Output Logic Low (SDA)
VA, VB, VW CA, CB CW
f = 1 kHz, measured to GND, Code = half scale f = 1 kHz, measured to GND, Code = half scale VA = VB = VDD/2 VDD = 5 V, VSS = 0 V VDD/VSS = 2.7 V/0 V or VDD/VSS = 2.5 V VDD = 5V, VSS = 0 V RPULL-UP = 2.2 k to VDD = 5 V, VSS = 0 V RPULL-UP = 2.2 k to VDD =5 V, VSS = 0 V 2.4 2.1
85 95
ICM VIH VIL VOH VOL
0.01
1
A V V V V V
0.8 4.9 0.4
Rev. 0 | Page 3 of 28
AD5251/AD5252
Parameter Leakage Current A0 Leakage Current Input Leakage Current (Other than WP and A0) Input Capacitance5 POWER SUPPLIES Single-Supply Power Range Dual-Supply Power Range Positive Supply Current Negative Supply Current EEMEM Data Storing Mode Current EEMEM Data Restoring Mode Current6 Power Dissipation7 Power Supply Sensitivity DYNAMIC CHARACTERISTICS5, 8 Bandwidth -3 dB Total Harmonic Distortion VW Settling Time Resistor Noise Voltage Digital Crosstalk Analog Coupling Symbol IWP IA0 II CI VDD VDD/VSS IDD ISS IDD_STORE IDD_RESTORE PDISS PSS VSS = 0 V VIH = VDD or VIL = GND VIH = VDD or VIL = GND, VDD = +2.5 V, VSS = -2.5 V VIH = VDD or VIL = GND VIH = VDD or VIL = GND VIH = VDD = 5 V or VIL = GND VDD = 5 V 10% VDD = 3 V 10% RAB = 1 k VA = 1 V rms, VB = 0 V, f = 1 kHz VA = VDD, VB = 0 V RWB = 500 , f = 1 kHz (thermal noise only) VA = VDD, VB = 0 V, measure VW with adjacent RDAC making full-scale change Signal input at A1 and measure the output at W3, f = 1 kHz 2.7 2.25 5 -5 35 2.5 0.075 0.025 0.04 Conditions WP = VDD A0 = GND VIN = 0 V or VDD 5 5.5 2.75 15 -15 Min Typ1 Max 5 3 1 Unit A A A pF V V A A mA mA mW %/% %/% MHz % s nV/Hz dB dB
-0.025 -0.04
0.01 0.02 4 0.05 0.2 3 -80 -72
BW THD tS eN_WB CT CAT
1 2
Typical represents the average reading at 25C and VDD = 5 V. Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic, except R-DNL of AD5252 1 k version at VDD = 2.7 V, IW = VDD/R for both VDD = 3 V or VDD = 5 V. 3 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V. DNL specification limits of 1 LSB maximum are guaranteed monotonic operating conditions. 4 Resistor Terminals A, B, and W have no limitations on polarity with respect to each other. 5 Guaranteed by design and not subject to production test. 6 cmd 0 NOP should be activated after cmd 1 to minimize IDD_READ current consumption. 7 PDISS is calculated from IDD x VDD = 5 V. 8 All dynamic characteristics use VDD = 5 V.
Rev. 0 | Page 4 of 28
AD5251/AD5252
10 k, 50 k, 100 k Versions. VDD = +3 V 10% or + 5 V 10%. VSS = 0 V or VDD/VSS = 2.5 V 10%. VA = +VDD, VB = 0 V, -40C < TA < +85C, unless otherwise noted. Table 2.
Parameter DC CHARACTERISTICS RHEOSTAT MODE Resolution Resistor Differential NL2 Resistor Nonlinearity2 Nominal Resistor Tolerance Resistance Temperature Coefficent Wiper Resistance Channel Resistance Matching DC CHARACTERISTICS POTENTIOMETER DIVIDER MODE Differential Nonlinearity3 Integral Nonlinearity3 Voltage Divider Temperature Coefficent Full-Scale Error Zero-Scale Error RESISTOR TERMINALS Voltage Range4 Capacitance5 Ax, Bx Capacitance5 Wx Common-Mode Leakage Current DIGITAL INPUTS and OUTPUTS Input Logic High Input Logic Low Output Logic High (SDA) Output Logic Low (SDA) Leakage Current A0 Leakage Current Input Leakage Current (Other than WP and A0) Input Capacitance5 POWER SUPPLIES Single-Supply Power Range DNL INL AD5251 AD5252 AD5251 AD5252 Code = half scale Code = full scale, AD5251 Code = full scale, AD5252 Code = zero scale, AD5251 Code = zero scale, AD5252 -0.5 -1 -0.5 -1.5 0.1 0.3 0.15 0.5 15 -0.3 -1 0.3 1.2 +0.5 +1 +0.5 +1.5 LSB LSB LSB LSB ppm/C LSB LSB LSB LSB V pF pF 1 A Symbol Conditions Min Typ1 Max Unit
N R-DNL R-INL RAB/RAB (RAB/RAB) x 106/T RW RAB1/RAB2
AD5251/AD5252 RWB, RWA = NC, AD5251 RWB, RWA = NC, AD5252 RWB, RWA = NC, AD5251 RWB, RWA = NC, AD5252 TA = 25C
-0.75 -1 -0.75 -2.5 -20
0.1 0.25 0.25 1 650
6/8 +0.75 +1 +0.75 +2.5 +20
Bits LSB LSB LSB LSB % ppm/C % %
IW = 1 V/R, VDD = 5 V IW = 1 V/R, VDD = 3 V RAB = 10 k, 50 k RAB = 100 k
75 200 0.15 0.05
130 300
(VW/VW) x 106/T VWFSE VWZSE
-1 -3 0 0 VSS
0 0 1 3 VDD
VA, VB, VW CA, CB CW ICM
f = 1 kHz, measured to GND, Code = half scale f = 1 kHz, measured to GND, Code = half scale VA = VB = VDD/2
85 95 0.01
VIH VIL VOH VOL IWP IA0 II CI VDD
VDD =5 V, VSS = 0 V VDD/VSS = +2.7 V/0 V or VDD/VSS = 2.5 V VDD = 5 V, VSS = 0 V VDD/VSS = +2.7 V/0 V or VDD/VSS =2.5 V RPULL-UP = 2.2 k to VDD = 5 V, VSS = 0 V RPULL-UP = 2.2 k to VDD = 5 V, VSS = 0 V WP = VDD A0 = GND VIN = 0 V or VDD
2.4 2.1 0.8 0.6 4.9 0.4 5 3 1 5
V V V V V V A A A pF V
VSS = 0 V
Rev. 0 | Page 5 of 28
2.7
5.5
AD5251/AD5252
Parameter Dual-Supply Power Range Positive Supply Current Negative Supply Current EEMEM Data Storing Mode Current EEMEM Data Restoring Mode Current6 Power Dissipation7 Power Supply Sensitivity DYNAMIC CHARACTERISTICS5, 8 -3 dB Bandwidth Total Harmonic Distortion VW Settling Time Resistor Noise Voltage Digital Crosstalk Symbol VDD/VSS IDD ISS IDD_STORE IDD_RESTORE PDISS PSS Conditions VIH = VDD or VIL = GND VIH = VDD or VIL = GND, VDD = +2.5 V, VSS = -2.5 V VIH = VDD or VIL = GND, TA = 0C to 85C VIH = VDD or VIL = GND, TA = 0C to 85C VIH = VDD = 5 V or VIL = GND VDD = 5 V 10% VDD = 3 V 10% RAB = 10 k/50 k/100 k VA = 1 Vrms, VB = 0 V, f = 1 kHz VA = VDD, VB = 0 V, RAB = 10 k/50 k/100 k 10 k/50 k/100 k, code = midscale, f = 1 kHz (thermal noise only) VA = VDD, VB = 0 V, Measure VW with adjacent RDAC making full scale change Signal input at A1 and measure output at W3, f = 1kHz Min 2.25 Typ1 5 -5 35 2.5 0.075 +0.005 +0.01 Max 2.75 15 -15 Unit V A A mA mA mW %/% %/% kHz % s nV/Hz dB
-0.005 -0.01
+0.002 +0.002 400/80/40 0.05 1.5/7/14 9/20/29 -80
BW THDW tS eN_WB CT
Analog Coupling
CAT
-72
dB
1 2
Typical represents the average reading at 25C and VDD = 5 V. Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic, except R-DNL of AD5252 1 k version at VDD = 2.7 V, IW = VDD/R for both VDD = 3 V or VDD = 5 V. 3 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V. DNL specification limits of 1 LSB maximum are guaranteed monotonic operating conditions. 4 Resistor Terminals A, B, and W have no limitations on polarity with respect to each other. 5 Guaranteed by design and not subject to production test. 6 cmd 0 NOP should be activated after cmd 1 to minimize IDD_READ current consumption. 7 PDISS is calculated from IDD x VDD = 5 V. 8 All dynamic characteristics use VDD = 5 V.
Rev. 0 | Page 6 of 28
AD5251/AD5252
INTERFACE TIMING CHARACTERISTICS
Guaranteed by design, not subject to production test. See Figure 3 for location of measured values. All input control voltages are specified with tR = tF = 2.5 ns (10% to 90% of 3 V), and timed from a voltage level of 1.5 V. Switching characteristics are measured using both VDD = 3 V and 5 V. Table 3. Interface Timing and EEMEM Reliability Characteristics (All Parts).
Parameter INTERFACE TIMING SCL Clock Frequency tBUF Bus Free Time between STOP and START tHD;STA Hold Time (Repeated START) tLOW Low Period of SCL Clock tHIGH High Period of SCL Clock tSU;STA Setup Time For START Condition tHD;DAT Data Hold Time tSU;DAT Data Setup Time tF Fall Time of Both SDA and SCL Signals tR Rise Time of Both SDA and SCL Signals tSU;STO Setup Time for STOP Condition EEMEM Data Storing Time EEMEM Data Restoring Time at Power-On1 EEMEM Data Restoring Time Upon Restore Command or RESET Operation1 EEMEM Rewritable Time (delay time after Power On or RESET before EEMEM can be written) FLASH/EE MEMORY RELIABILITY Endurance2 Data Retention3 100 100 kCycles Years Symbol fSCL t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 tEEMEM_STORE tEEMEM_RESTORE1 VDD rise time dependent. Measure without decoupling capacitors at VDD and VSS. VDD = 5 V 0.6 26 300 After this period, the first clock pulse is generated Conditions Min Typ Max 400 1.3 0.6 1.3 0.6 0.6 0 100 300 300 0.9 Unit kHz s s s s s s ns ns ns s ms s
tEEMEM_RESTORE2 tEEMEM_REWRITE
300 540
s s
1
During power-up, all outputs preset to midscale before restoring to the final EEMEM contents. RDAC0 has the shortest, whereas RDAC3 has the longest EEMEM data restoring time. Retention lifetime equivalent at junction temperature TJ = 55C per JEDEC Std. 22, Method A117. Retention lifetime based on an activation energy of 0.6 eV derates with junction temperature. 3 When the part is not in operation, the SDA and SCL pins should be pulled to high. When these pins are pulled to low, the I2C interface at these pins conducts current of about 0.8 mA at VDD = 5.5 V and 0.2 mA at VDD = 2.7 V.
2
Rev. 0 | Page 7 of 28
AD5251/AD5252 ABSOLUTE MAXIMUM RATINGS
TA = 25C, unless otherwise noted . Table 4.
Parameter VDD to GND VSS to GND VDD to VSS VA, VB, VW to GND Maximum Current IWB, IWA Pulsed IWB Continuous (RWB 1 k, A Open)1 IWA Continuous (RWA 1 k, B Open)1 IAB Continuous (RAB = 1 k/10 k/50 k/100 k)1 Digital Inputs and Output Voltage to GND Operating Temperature Range Maximum Junction Temperature (TJ MAX) Storage Temperature Lead Temperature (Soldering,10 sec) Vapor Phase (60 sec) Infrared (15 sec) TSSOP-14 Thermal Resistance2 JA Rating -0.3 V, +7 V +0.3 V, -7 V 7V VSS, VDD 20 mA 5 mA 5 mA 5 mA/500 A/ 100 A/50 A 0 V, 7 V -40C to +85C 150C -65C to +150C 300C 215C 220C 136C/W
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
1
Maximum terminal current is bounded by the maximum applied voltage across any two of the A, B, and W terminals at a given resistance, the maximum current handling of the switches, and the maximum power dissipation of the package. VDD = 5 V. 2 Package power dissipation = (TJMAX - TA)/JA.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev.0 | Page 8 of 28
AD5251/AD5252 PIN CONFIGURATION AND FUNCTION DESCRIPTION
VDD AD0 WP W1 B1 A1 SDA
1 2 3 4 5 6 7 14 W3 13 B3
AD5251/ AD5252
TOP VIEW (Not to Scale)
12 A3 11 AD1 10 DGND
03823-0-002
9 8
SCL VSS
Figure 2. AD5251/AD5252 in TSSOP-14
Table 5. Pin Function Descriptions
Pin No. 1 Mnemonic VDD Description Positive Power Supply Pin. Connect +2.7 V to +5 V for single supply or 2.7 V for dual supply, where VDD - VSS 5.5 V. VDD must be able to source 35 mA for 26 ms when storing data to EEMEM. I2C Device Address 0. AD0 and AD1 allow four AD5251/AD5252s to be addressed. Write Protect, Active Low. VWP VDD + 0.3 V. Wiper Terminal of RDAC1. VSS VW1 VDD.1 B Terminal of RDAC1. VSS VB1 VDD.1 A Terminal of RDAC1. VSS VA1 VDD.1 Serial Data Input/Output Pin. Shifts in one bit at a time on positive clock edges. MSB loaded first. Open-drain MOSFET requires pull-up resistor. Negative Supply. Connect to 0 V for single supply or -2.7 V for dual supply, where VDD - VSS +5.5 V. If VSS is used, other than grounded, in dual supply, VSS must be able to sink 35 mA for 26 ms when storing data to EEMEM. Serial Input Register Clock Pin. Shifts in one bit at a time on positive clock edges. VSCL (VDD + 0.3 V). Pull-up resistor is recommended for SCL to ensure minimum power. Digital Ground. Connect to system analog ground at a single point. I2C Device Address 1. AD0 and AD1 allow four AD5251/AD5252s to be addressed. A Terminal of RDAC3. VSS VA3 VDD.1 B Terminal of RDAC3. VSS VB3 VDD.1 W Terminal of RDAC3. VSS VW3 VDD.1
2 3 4 5 6 7 8
AD0 WP W1 B1 A1 SDA VSS
9 10 11 12 13 14
SCL DGND AD1 A3 B3 W3
1
For quad-channel device software compatibility, the dual potentiometers in the parts are designated as RDAC1 and RDAC3.
I2C INTERFACE TIMING DIAGRAM
SCL
t8
t9
t6
t2
t3 t8 t9
t4
t5
t7
t10
P
S
P
Figure 3. I2C Timing Diagram
Rev. 0 | Page 9 of 28
03823-0-003
SDA
t1
AD5251/AD5252 I2C INTERFACE GENERAL DESCRIPTION
FROM MASTER TO SLAVE FROM SLAVE TO MASTER S = START CONDITION P = STOP CONDITION A = ACKNOWLEDGE (SDA LOW) A = NOT ACKNOWLEDGE (SDA HIGH) R/W = READ ENABLE AT HIGH AND WRITE ENABLE AT LOW S SLAVE ADDRESS (7-BIT) R/W A INSTRUCTIONS (8-BIT) A DATA (8-BIT) A/A P
03823-0-004
0 WRITE
DATA TRANSFERRED (N BYTES + ACKNOWLEDGE)
Figure 4. I2C--Master Writing Data to Slave
S
SLAVE ADDRESS (7-BIT)
R/W
A
DATA (8-BIT)
A
DATA (8-BIT)
A
P
03823-0-005
1 READ
DATA TRANSFERRED (N BYTES + ACKNOWLEDGE)
Figure 5. I2C--Master Reading Data from Slave
S
SLAVE ADDRESS (7-BIT)
R/W
A
DATA
A/A
S
SLAVE ADDRESS
R/W
A
DATA
A/A
P
03823-0-006
READ OR WRITE
(N BYTES + ACKNOWLEDGE)
REPEATED START
READ OR WRITE
(N BYTES + ACKNOWLEDGE)
DIRECTION OF TRANSFER MAY CHANGE AT THIS POINT
Figure 6. I2C--Combined Write/Read
Rev. 0 | Page 10 of 28
AD5251/AD5252 I2C INTERFACE DETAIL DESCRIPTION
FROM MASTER TO SLAVE FROM SLAVE TO MASTER S = START CONDITION P = STOP CONDITION A = ACKNOWLEDGE (SDA LOW) A = NOT ACKNOWLEDGE (SDA HIGH) R/W = READ ENABLE AT HIGH AND WRITE ENABLE AT LOW CMD/REG = COMMAND ENABLE BIT, LOGIC HIGH/REGISTER ACCESS BIT, LOGIC LOW EE/RDAC = EEMEM REGISTER, LOGIC HIGH/RDAC REGISTER, LOGIC LOW A4, A3, A2, A1, A0 = RDAC/EEMEM REGISTER ADDRESSES S 0 1 0 1 1 A D 1 A D 0 0 A CMD/ REG 0 EE/ RDAC A 4 A 3 A 2 A 1 A 0 A DATA A/ A P
SLAVE ADDRESS 0 WRITE 0 REG
INSTRUCTIONS AND ADDRESS
(1 BYTE + ACKNOWLEDGE)
Figure 7. Single Write Mode
03823-0-007
S
0
1
0
1
1
A D 1
A D 0
0
A
CMD/ REG
0
EE/ RDAC
A 4
A 3
A 2
A 1
A 0
A
RDAC1 DATA
A
RDAC3 DATA
A/ A
P
RDAC SLAVE ADDRESS 0 WRITE 0 REG
RDAC INSTRUCTIONS AND ADDRESS
(N BYTES + ACKNOWLEDGE)
Figure 8. Consecutive Write Mode
Table 6. Addresses for Writing Data Byte Contents to RDAC Registers (R/W = 0, CMD/REG = 0, EE/RDAC = 0)
A4 0 0 0 0 0 : 0 A3 0 0 0 0 0 : 1 A2 0 0 0 0 1 : 1 A1 0 0 1 1 0 : 1 A0 0 1 0 1 0 : 1 RDAC Reserved RDAC1 Reserved RDAC3 Reserved Reserved Data Byte Description 6- or 8 bit wiper setting (2 MSBs of AD5251 are X) 6- or 8 bit wiper setting (2 MSBs of AD5251 are X)
RDAC/EEMEM WRITE
Setting the wiper position requires an RDAC write operation. The single write operation is shown in Figure 7, and the consecutive write operation is shown in Figure 8. In the consecutive write operation, if the RDAC is selected and the address starts at 00001, the first data byte goes to RDAC1 and the second data byte goes to RDAC3. The RDAC address is shown in Table 6. While the RDAC wiper setting is controlled by a specific RDAC register, each RDAC register corresponds to a specific EEMEM location, which provides nonvolatile wiper storage functionality. The addresses are shown in Table 7. The single and consecutive write operations apply also to EEMEM write operations. There are 12 nonvolatile memory locations: EEMEM4 to EEMEM15. Users can store a total of 12 bytes of information, such as memory data for other components, look-up tables, or system identification information. In a write operation to the EEMEM registers, the device disables the I2C interface during the internal write cycle. Acknowledge polling is required to determine the completion of the write cycle. See EEMEM Write-Acknowledge Polling.
Rev. 0 | Page 11 of 28
03823-0-008
AD5251/AD5252
Table 7. Addresses for Writing (Storing) RDAC Settings and User-Defined Data to EEMEM Registers (R/W = 0, CMD/REG = 0, EE/RDAC = 1)
A4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1
selected previously, readback starts with Address N, followed by N + 1, and so on. Figure 10 illustrates a random RDAC or EEMEM read operation. This operation lets users specify which RDAC or EEMEM register is read by first issuing a dummy write command to change the RDAC address pointer, and then proceeding with the RDAC read operation at the new address location. Table 8. Addresses for Reading (Restoring) RDAC Settings and User Data from EEMEM (R/W = 1, CMD/REG = 0, EE/RDAC = 1)
A4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 A2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Data Byte Description Reserved Read RDAC1 Setting from EEMEM1 Reserved Read RDAC3 Setting from EEMEM3 Read user data from EEMEM4 Read user data from EEMEM5 Read user data from EEMEM6 Read user data from EEMEM7 Read user data from EEMEM8 Read user data from EEMEM9 Read user data from EEMEM10 Read user data from EEMEM11 Read user data from EEMEM12 Read user data from EEMEM13 Read user data from EEMEM14 Read user data from EEMEM15
A3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
A2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
A1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
A0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Data Byte Description Reserved Store RDAC1 setting to EEMEM11 Reserved Store RDAC3 setting to EEMEM31 Store user data to EEMEM4 Store user data to EEMEM5 Store user data to EEMEM6 Store user data to EEMEM7 Store user data to EEMEM8 Store user data to EEMEM9 Store user data to EEMEM10 Store user data to EEMEM11 Store user data to EEMEM12 Store user data to EEMEM13 Store user data to EEMEM14 Store user data to EEMEM15
User can store any of the 64 RDAC settings for AD5251 or any of the 256 RDAC settings for AD5252.
RDAC/EEMEM Read
The AD5251/AD5252 provide two different RDAC or EEMEM read operations. For example, Figure 9 shows the method of reading the RDAC0 to RDAC3 contents without specifying the address, assuming Address RDAC0 was already selected from the previous operation. If RDAC_N, other than Address 0, is
S 0 1 0 1 1 A D 1 A D 0 1 A
RDAC1 EEMEM OR REGISTER DATA
A
RDAC3 EEMEM OR REGISTER DATA
A
P
RDAC SLAVE ADDRESS 1 READ
(N BYTES + ACKNOWLEDGE)
Figure 9. RDAC Current Read (Restricted to Previously Selected Address Stored in the Register).
S
SLAVE ADDRESS
0
A
INSTRUCTION AND ADDRESS
A
S
SLAVE ADDRESS
1
A
RDAC OR EEMEM DATA
03823-0-009
A/A
P
(N BYTES + ACKNOWLEDGE) 0 WRITE REPEATED START 1 READ
Figure 10. RDAC or EEMEM Random Read
Rev. 0 | Page 12 of 28
03823-0-010
AD5251/AD5252
RDAC/EEMEM Quick Commands
The AD5251/AD5252 feature 12 quick commands that facilitate easy manipulation of RDAC wiper settings and provide RDACto-EEMEM storing and restoring functions. The command
FROM MASTER TO SLAVE FROM SLAVE TO MASTER S = START CONDITION P = STOP CONDITION A = ACKNOWLEDGE (SDA LOW) A = NOT ACKNOWLEDGE (SDA HIGH) AD1, AD0 = I2C DEVICE ADDRESS BITS. MUST MATCH WITH THE LOGIC STATES AT PINS AD1, AD0 R/W = READ ENABLE BIT, LOGIC HIGH/WRITE ENABLE BIT, LOGIC LOW CMD/REG = COMMAND ENABLE BIT, LOGIC HIGH/REGISTER ACCESS BIT, LOGIC LOW C3, C2, C1, C0 = COMMAND BITS A2, A1, A0 = RDAC/EEMEM REGISTER ADDRESSES S 0 1 0 1 1 A D 1 A D 0 0 A CMD/ REG C 3 C 2 C 1 C 0 A 2 A 1 A 0 A P
format is shown in Figure 11 and the command descriptions are shown in Table 9.
RDAC SLAVE ADDRESS 0 WRITE 1 CMD
Figure 11. RDAC Quick Command Write (Dummy Write)
Table 9. RDAC-to-EEMEM Interface and RDAC Operation Quick Command Bits (CMD/REG = 1, A2 = 0)
C3 0 0 0 0 0 0 0 0 1 1 1 1 1 : 1 C2 0 0 0 0 1 1 1 1 0 0 0 0 1 : 1 C1 0 0 1 1 0 0 1 1 0 0 1 1 0 : 1 C0 0 1 0 1 0 1 0 1 0 1 0 1 0 : 1 Command Description NOP Restore EEMEM (A1, A0) to RDAC (A1, A0)1 Store RDAC (A1, A0) to EEMEM (A1, A0) Decrement RDAC (A1, A0) 6 dB Decrement all RDACs 6 dB Decrement RDAC (A1, A0) one step Decrement all RDACs one step Reset: Restore EEMEMs to all RDACs Increment RDACs (A1, A0) 6 dB Increment all RDACs 6 dB Increment RDACs (A1, A0) one step Increment all RDACs one step Reserved Reserved
1
This command leaves the device in the EEMEM read power state, which consumes power. Users should issue the NOP command to return the device to the idle state.
Table 10. Address Table for Reading Tolerance (CMD/REG = 0, EE/RDAC = 1, A4 = 1)
A4 0 : 1 1 1 1 1 1 1 A3 0 : 1 1 1 1 1 1 1 A2 0 : 0 0 0 1 1 1 1 A1 0 : 0 1 1 0 0 1 1 A0 0 : 1 0 1 0 1 0 1 Data Byte Description Reserved Reserved Sign and 7-bit integer values of RDAC1 tolerance (read only) 8-bit decimal value of RDAC1 tolerance (read only) Reserved Reserved Sign and 7-bit integer values of RDAC3 tolerance (read only) 8-bit decimal value of RDAC3 tolerance (read only)
Rev. 0 | Page 13 of 28
03823-0-011
AD5251/AD5252
A D7 SIGN D6 26 D5 25 D4 24 D3 23 D2 22 D1 21 D0 20 A D7 2-1 D6 2-2 D5 2-3 D4 2-4 D3 2-5 D2 2-6 D1 2-7 D0 2-8
03823-0-012
A
SIGN
7 BITS FOR INTEGER NUMBER
8 BITS FOR DECIMAL NUMBER
Figure 12. Format of Stored Tolerance in Sign Magnitude Format with Bit Position Descriptions. (Unit is percent. Only data bytes are shown.)
RAB Tolerance Stored in Read-Only Memory
The AD5251/AD5252 feature patented RAB tolerances storage in the nonvolatile memory. The tolerance of each channel is stored in the memory during the factory production and can be read by users at any time. The knowledge of stored tolerance, which is the average of RAB over all codes (see Figure 28), allows users to predict RAB accurately. This feature is valuable for precision, rheostat mode, and open-loop applications where knowledge of absolute resistance is critical. The stored tolerances reside in the read-only memory, and are expressed as a percentage. The tolerance is stored in two memory locations (see Table 10). The data format of the tolerance is in sign magnitude binary form. An example is shown in Figure 11. In the first memory location, the MSB is designated for the sign (0 = + and 1= -) and the 7 LSBs are designated for the integer portion of the tolerance. In the second memory location, all eight data bits are designated for the decimal portion of tolerance. As shown in Table 10 and Figure 12 for example, if the rated RAB = 10 k and the data readback from Address 11000 shows 0001 1100 and Address 11001 shows 0000 1111, then RDAC0 tolerance can be calculated as MSB: 0 = + Next 7 MSB: 001 1100 = 28 8 LSB: 0000 1111 = 15 x 2-8 = 0.06 Tolerance = +28.06% and therefore RAB_ACTUAL = 12.806 k
EEMEM Write-Acknowledge Polling
After each write operation to the EEMEM registers, an internal write cycle begins. The I2C interface of the device is disabled. To determine if the internal write cycle is complete and the I2C interface is enabled, interface polling can be executed. I2C interface polling can be conducted by sending a start condition followed by the slave address + the write bit. If the I2C interface responds with an ACK, the write cycle is complete and the interface is ready to proceed with further operations. Otherwise, I2C interface polling can be repeated until it succeeds. Commands 2 and 7 also require acknowledge polling.
EEMEM Write Protection
Setting the WP pin to a logic LOW after EEMEM programming protects the memory and RDAC registers from future write operations. In this mode, the EEMEM and RDAC read operations operate as normal. When write protection is enabled, Command 1 (Restore from EEMEM to RDAC) and Command 7 (Reset) function normally to allow RDAC settings to be refreshed from the EEMEM to the RDAC registers.
Rev. 0 | Page 14 of 28
AD5251/AD5252 I2C COMPATIBLE 2-WIRE SERIAL BUS
1 SCL SDA 0 1 0 1 X 1 AD1 AD0 R/W ACK. BY AD525x X X X X X X X D7 D6 ACK. BY AD525x D5 D4 D3 D2 D1 D0 ACK. BY AD525x STOP BY MASTER 9 1 9 1 9
START BY MASTER
FRAME 1 SLAVE ADDRESS BYTE
FRAME 2 INSTRUCTION BYTE
FRAME 1 DATA BYTE
Figure 13. General I2C Write Pattern
1 SCL SDA 0 1 0 1 1 AD1 AD0 R/W
9
1 D7 D6 D5 D4 D3 D2 D1 D0
9
START BY MASTER
FRAME 1 SLAVE ADDRESS BYTE
FRAME 2 RDAC REGISTER
STOP BY MASTER
Figure 14. General I2C Read Pattern
The first byte of the AD5251/AD5252 is a slave address byte (see Figure 12 and Figure 13). It has a 7-bit slave address and an R/W bit. The 5 MSBs of the slave address are 01011, and the following 2 LSBs are determined by the states of the AD1 and AD0 pins. AD1 and AD0 allow the user to place up to four parts on one bus. AD5251/AD5252 can be controlled via an I2C compatible serial bus, and are connected to this bus as slave devices. The 2-wire I2C serial bus protocol (see Figure 13 and Figure 14) follows: 1. The master initiates a data transfer by establishing a start condition, such that SDA goes from high to low while SCL is high (see Figure 13). The following byte is the slave address byte, which consists of the 5 MSBs of a slave address defined as 01011. The next two bits are AD1 and AD0, I2C device address bits. Depending on the states of their AD1 and AD0 bits, four parts can be addressed on the same bus. The last LSB, the R/W bit, determines whether data is read from or written to the slave device. The slave whose address corresponds to the transmitted address responds by pulling the SDA line low during the ninth clock pulse (this is called an acknowledge bit). At this stage, all other devices on the bus remain idle while the selected device waits for data to be written to or read from its serial register. 2. In the write mode (except when restoring EEMEM to the RDAC register), there is an instruction byte that follows the slave address byte. The MSB of the instruction byte is labeled CMD/REG. MSB = 1 enables CMD, the command instruction byte; MSB = 0 enables general register writing. The third MSB in the instruction byte, labeled EE/RDAC, is true only when MSB = 0 or is in general writing mode. EE enables the EEMEM register and REG enables the RDAC register. The 5 LSBs, A4 to A0, designate the
Rev.0 | Page 15 of 28
addresses of the EEMEM and RDAC registers, (see Figure 7 and Figure 8). When MSB = 1 or when in CMD mode, the four bits following MSB are C3 to C1, which correspond to 12 predefined EEMEM controls and quick commands; there also are four factory reserved commands. The 3 LSBs--A2, A1, and A0--are four addresses, but only 001 and 011 are used for RDAC1 and RDAC3, respectively (see Figure 10). After acknowledging the instruction byte, the last byte in the write mode is the data byte. Data is transmitted over the serial bus in sequences of nine clock pulses (eight data bits followed by an acknowledge bit). The transitions on the SDA line must occur during the low period of SCL and remain stable during the high period of SCL (see Figure 13). 3. In current read mode, the RDAC0 data byte immediately follows the acknowledgment of the slave address byte. After an acknowledgement, RDAC1 follows, then RDAC2, and so on (there is a slight difference in write mode, where the last eight data bits representing RDAC3 data are followed by a no acknowledge bit). Similarly, the transitions on the SDA line must occur during the low period of SCL and remain stable during the high period of SCL (see Figure 14). Another reading method, random read method, is shown in Figure 10. When all data bits have been read or written, a stop condition is established by the master. A stop condition is defined as a low-to-high transition on the SDA line while SCL is high. In write mode, the master pulls the SDA line high during the 10th clock pulse to establish a stop condition (see Figure 13). In read mode, the master issues a no acknowledge for the ninth clock pulse, i.e., the SDA line remains high. The master then brings the SDA line low before the 10th clock pulse, which goes high to establish a stop condition (see Figure 14).
4.
03823-0-014
ACK. BY AD525x
NO ACK. BY MASTER
03823-0-013
AD5251/AD5252 TYPICAL PERFORMANCE CHARACTERISTICS
1.0 0.8 0.6 0.4
R-INL (LSB)
1.0 0.8 TA = -40C, +25C, +85C, +125C
TA = -40C, +25C, +85C, +125C
0.6 0.4 0.2
0.2 0 -0.2 -0.4 -0.6 -0.8
03823-0-015
INL (LSB)
0 -0.2 -0.4 -0.6 -0.8
03823-0-018
03823-0-020 03823-0-019
-1.0 0 32 64 96 128 160 192 224 256 CODE (Decimal)
-1.0 0 32 64 96 128 160 192 224 256 CODE (Decimal)
Figure 15. R-INL vs. Code
Figure 18. DNL vs. Code
1.0 0.8 0.6
SUPPLY CURRENT (A)
10 TA = -40C, +25C, +85C, +125C 8 6 4 2 0 -2 -4 -6 -8
03823-0-016
IDD @ VDD = +5.5V
0.4
R-DNL (LSB)
0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 32 64 96 128 160 192 224 256 CODE (Decimal)
IDD @ VDD = +2.7V
ISS @ VDD = +2.7V, VSS = -2.7V
-10 -40
-20
0
20
40
60
80
100
120
TEMPERATURE (C)
Figure 16. R-DNL vs. Code
Figure 19. Supply Current vs. Temperature
1.0 0.8 0.6 0.4
INL (LSB)
10 TA = -40C, +25C, +85C, +125C 1 VDD = 5.5V
0 -0.2 -0.4 -0.6 -0.8
03823-0-017
IDD (mA)
0.2
0.1
0.01 VDD = 2.7V
0.001
-1.0 0 32 64 96 128 160 192 224 256 CODE (Decimal)
0.0001 0 1 2 3 4 5 6 DIGITAL INPUT VOLTAGE (V)
Figure 17. INL vs. Code
Figure 20. Supply Current vs. Digital Input Voltage, TA = 25C
Rev.0 | Page 16 of 28
AD5251/AD5252
240
POTENTIOMETER MODE TEMPCO (ppm/C)
30 DATA = 0x00 VDD = 2.7V TA = 25C VDD = 5V TA = -40C/+85C VA = VDD VB = 0V
220 200 180 160
RWB ()
25
20
140 120 100 80 60 40 20
03823-0-021
15
VDD = 5.5V TA = 25C
10
5
0
1
2
3 VBIAS (V)
4
5
6
0
32
64
96
128
160
192
224
256
CODE (Decimal)
Figure 21. Wiper Resistance vs. VBIAS
Figure 24. AD5252 Potentiometer Mode Tempco VWB/T vs. Code
6
0 -6
0xFF 0x40 0x80
4
-12 -18
0x20 0x10
2
RWB (%)
0
GAIN (dB)
-24 -30 -36 -42 0x08 0x04 0x02 0x01 0x00
-2
-48 -54
03823-0-022
-4
-20
0
20
40
60
80
100
120
10
100
1k
10k
100k
1M
10M
TEMPERATURE (C)
FREQUENCY (Hz)
Figure 22. Change of RAB vs. Temperature
Figure 25. AD5252 Gain vs. Frequency vs. Code, RAB = 1 k
90
RHEOSTAT MODE TEMPCO (ppm/C)
0
0xFF 0x80 0x40 0x20 0x10 0x08 0x04 0x01 0x00 0x02
03823-0-026
80 70 60 50 40 30 20 10
VDD = 5V TA = -40C/+85C VA = VDD VB = 0V
-6 -12 -18
GAIN (dB)
-24 -30 -36 -42 -48 -54
0
32
64
96
128
160
192
224
256
03823-0-023
0 CODE (Decimal)
-60 10 100 1k 10k 100k 1M 10M FREQUENCY (Hz)
Figure 23. AD5252 Rheostat Mode Tempco RWB/T vs. Code
Figure 26. AD5252 Gain vs. Frequency vs. Code, RAB = 10 k
Rev. 0 | Page 17 of 28
03823-0-025
-6 -40
-60
03823-0-024
0
0
AD5251/AD5252
0 -6 -12 -18 0xFF 0x80 0x40 0x20 0.8 1.2 TA = 25C 1.0
GAIN (dB)
IDD (mA)
-24 -30 -36 -42 -48 -54 -60 10 100 1k 0x02
0x10 0x08 0x04 0x01 0x00
VDD = 5.5V 0.6
0.4
0.2
VDD = 2.7V
03823-0-026
10k
100k
1M
10M
1
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
CLOCK FREQUENCY (Hz)
Figure 27. AD5252 Gain vs. Frequency vs. Code, RAB = 50 k
Figure 30. Supply Current vs. Digital Input Clock Frequency
0 0x80 -6 -12 -18 0x40 0x20 0x10 0x08 0x04 0x02 -42 0x01 -48 -54
03823-0-028
0xFF
CLK VDD = 5V
GAIN (dB)
-24 -30 -36
VW DIGITAL FEEDTHROUGH
-60 10 100 1k 10k 100k 1M FREQUENCY (Hz)
10M
Figure 28. AD5252 Gain vs. Frequency vs. Code, RAB = 100 k
Figure 31. Clock Feedthrough and Midscale Transition Glitch
100 VDD = 5.5V 80 100k 60 40 20 10k
MIDSCALE PRESET RESTORE RDAC3 SETTING TO 0x3F MIDSCALE PRESET VDD = VA1 = VA3 = 3.3V GND = VB1 = VB3
03823-0-029
RESTORE RDAC1 SETTING TO 0x3F
VDD (NO DECOUPLING CAPS) VWB1 (0x3F STORED IN EEMEM) VWB3 (0x3F STORED IN EEMEM)
RAB ()
1k 0 -20 50k -40 -60 -80 -100 0 32 64 96 128 160 192 224 256 CODE (Decimal)
Figure 29. AD5252 RAB vs. Code, TA = 25C
Figure 32 .tEEMEM_RESTORE
Rev. 0 | Page 18 of 28
03823-0-032
03823-0-031
0x00
03823-0-030
0
AD5251/AD5252
6 6
5
RAB = 1k
5
RAB = 1k
THEORETICAL IWB_MAX (mA)
4
VA = VB = OPEN TA = 25C
THEORETICAL IWB_MAX (mA)
4
VA = VB = OPEN TA = 25C
3
3
2
RAB = 10k
2
RAB = 10k
1
RAB = 50k RAB = 100k
03823-0-033
1
RAB = 50k RAB = 100k 0 32 64 96 128 160 192 224 256
03823-0-034
0 0
0
8
16
24
32
40
48
56
64
CODE (Decimal)
CODE (Decimal)
Figure 33. AD5251 IWBmax vs. Code
Figure 34. AD5252 IWBmax vs. Code
Rev. 0 | Page 19 of 28
AD5251/AD5252 OPERATIONAL OVERVIEW
The AD5251/AD5252 are dual-channel digital potentiometers in 1 k, 10 k, 50 k, or 100 k that allow 64 and 256 linear resistance step adjustments. The AD5251/AD5252 employ double-gate CMOS EEPROM technology that allows resistance settings and user-defined data to be stored in the EEMEM registers. The EEMEM is nonvolatile, such that settings remain when power is removed. The RDAC wiper settings are restored from the non-volatile memory settings during device power-up and can also be restored at any time during operation. The AD5251/AD5252 resistor wiper positions are determined by the RDAC register contents. The RDAC register acts like a scratch-pad register, allowing unlimited changes of resistance settings. RDAC register contents can be changed using the device's serial I2C interface. The format of the data-words and the commands to program the RDAC registers are discussed in the I2C Interface Detail Description section. The four RDAC registers have corresponding EEMEM memory locations that provide nonvolatile storage of resistor wiper position settings. The AD5251/AD5252 provide commands to store the RDAC register contents to their respective EEMEM memory locations. During subsequent power-on sequences, the RDAC registers are automatically loaded with the stored value. Whenever the EEMEM write operation is enabled, the device activates the internal charge pump and raises the EEMEM cell gate bias voltage to a high level, essentially erasing the current content in the EEMEM register and allowing subsequent storage of the new content. Saving data to an EEMEM register consumes about 35 mA of current and lasts about 26 ms. Because of charge pump operation, all RDAC channels may experience noise coupling during the EEMEM writing operation. The EEMEM restore time in power-up or during operation is about 300 s. Note that the power up EEMEM refresh time depends on how fast VDD reaches its final value. As a result, any supply voltage decoupling capacitors limit the EEMEM restore time during power-up. Figure 32 shows the power up profile where VDD, without any decoupling capacitors connected to it, is applied with a digital signal. The device initially resets the measured RDACs to midscale before reaching their final values during EEMEM restoration. In addition, users should issue a NOP Command 0 immediately after using Command 1 to restore the EEMEM setting to RDAC, to minimize supply current dissipation. Directly reading user data from EEMEM does not require similar NOP command execution. In addition to the movement of data between RDAC registers and EEMEM memory, the AD5251/AD5252 provide other shortcut commands that facilitate the users' programming needs, as shown in Table 11.
Rev. 0 | Page 20 of 28
Table 11. AD5251/AD5252 Quick Commands
Commmand 0 1 Description NOP Restore EEMEM content to RDAC. User should issue NOP immediately after this command to conserve power. Store RDAC register setting to EEMEM. Decrement RDAC 6 dB (shift data bits right). Decrement all RDACs 6 dB (shift all data bits right). Decrement RDAC one step. Decrement all RDACs one step. Reset EEMEM contents to all RDACs. Increment RDAC 6 dB (shift data bits left). Increment All RDACs 6 dB (shift all data bits left). Increment RDAC one step. Increment all RDACs one step. Reserved.
2 3 4 5 6 7 8 9 10 11 12-15
LINEAR INCREMENT AND DECREMENT COMMANDS
The increment and decrement commands (10, 11, 5, and 6) are useful for linear step adjustment applications. These commands simplify microcontroller software coding by allowing the controller to send just an increment or decrement command to the AD5251/AD5252. The adjustments can be directed to an individual RDAC or to all four RDACs.
6 dB ADJUSTMENTS (DOUBLING/HALVING WIPER SETTING)
The AD5251/AD5252 accommodates 6 dB adjustments of the RDAC wiper positions by shifting the register contents to left/right for increment/decrement operations, respectively. Commands 3, 4, 8, and 9 can be used to increment or decrement the wiper positions in 6 dB steps synchronously or asynchronously. Incrementing the wiper position by +6 dB is essentially doubling the RDAC register value, while decrementing by -6 dB is halving the register content. Internally, the AD5251/AD5252 use shift registers to shift the bits left and right to achieve a 6 dB increment or decrement. The maximum number of adjustments is nine and eight steps for increment from zero scale and decrement from full scale, respectively. These functions are useful for various audio/video level adjustments, especially for white LED brightness settings where human visual responses are more sensitive to large than small adjustments.
AD5251/AD5252
DIGITAL INPUT/OUTPUT CONFIGURATION
SDA is a digital input/output with an open-drain MOSFET that requires a pull-up resistor for proper communication. On the other hand, SCL and WP are digital inputs for which pull-up resistors are recommended to minimize the MOSFETs cross conduction current when the driving signals are lower than VDD. SCL and WP have ESD protection diodes, as shown in Figure 35 and Figure 36. WP can be permanently tied to VDD without a pull-up resistor if the write-protect feature is not used. If WP is left floating, an internal current source pulls it low to enable write-protect. In applications where the device is not being programmed on a frequent basis, this allows the part to default to write-protect after any one-time factory programming or field calibration without the use of an on board pull-down resistor. Because there are protection diodes on all these inputs, their signal levels must not be greater than VDD to prevent forward biasing of the diodes.
VDD
Table 12. Multiple Devices Addressing
AD1 0 0 1 1 AD0 0 1 0 1 Device Addressed U1 U2 U3 U4
+5V RP RP
SDA MASTER VDD SDA SCL AD1 U1 AD0 SDA SCL AD1 U2 AD0 VDD SDA SCL AD1 U3 AD0 VDD SDA SCL AD1 U4 AD0 SCL
Figure 37. Multiple AD5251/AD5252s on a Single Bus
TERMINAL VOLTAGE OPERATION RANGE
The AD5251/AD5252 are designed with internal ESD diodes for protection; these diodes also set the boundary of the terminal operating voltages. Positive signals present on Terminal A, B, or W that exceed VDD are clamped by the forward biased diode. Similarly, negative signals on Terminal A, B, or W that are more negative than VSS are also clamped (see Figure 38). In practice, users should not operate VAB, VWA, and VWB to be higher than the voltage across VDD to VSS, but VAB, VWA, and VWB have no polarity constraint.
VDD
SCL
GND
Figure 35. SCL Digital Input
VDD
03823-0-035
A
INPUTS
W B
03823-0-018
WP
03823-0-036
VSS
Figure 38. Maximum Terminal Voltages Set by VDD and VSS
GND
Figure 36. Equivalent WP Digital Input
POWER-UP AND POWER-DOWN SEQUENCES
Because the ESD protection diodes limit the voltage compliance at terminals A, B, and W (see Figure 38), it is important to power-on VDD/VSS before applying any voltage to Terminals A, B, and W. Otherwise, the diodes are forward-biased such that VDD/VSS are powered unintentionally and may affect the rest of the user's circuit. Similarly, VDD/VSS should be powered down last. The ideal power-up sequence is in the following order: GND, VDD, VSS, digital inputs, and VA/VB/VW. The order of powering VA, VB, VW, and the digital inputs is not important, as long as they are powered after VDD/VSS.
MULTIPLE DEVICES ON ONE BUS
The AD5251/AD5252 are equipped with two addressing pins, AD1 and AD0, that allow up to four AD5251/AD5252s to be operated on one I2C bus. To achieve this result, the states of AD1 and AD0 on each device must first be defined. An example is shown in Table 12 and Figure 37. In I2C programming, each device is issued a different slave address--01011(AD1)(AD0)-- to complete the addressing.
Rev. 0 | Page 21 of 28
03823-0-016
AD5251/AD5252
LAYOUT AND POWER SUPPLY BIASING
It is always a good practice to employ a compact, minimum lead-length layout design. The leads to the input should be as direct as possible, with a minimum conductor length. Ground paths should have low resistance and low inductance. Similarly, it is also good practice to bypass the power supplies with quality capacitors. Low equivalent series resistance (ESR) 1 F to 10 F tantalum or electrolytic capacitors should be applied at the supplies to minimize any transient disturbance and filter low frequency ripple. Figure 39 illustrates the basic supply bypassing configuration for the AD5251/AD5252.
AD5251/AD5252
VDD C3 + C1 10F C4 VSS + C2 10F 0.1F VSS GND
03823-0-039
SWA AX SW(2N-1)
RDAC WIPER REGISTER AND DECODER
RS
WX SW(2N-2)
RS
SW(1)
RS RS = RAB/2N
SW(0)
BX
VDD 0.1F
Figure 40. Equivalent RDAC Structure
PROGRAMMABLE RHEOSTAT OPERATION
If either the W-to-B or W-to-A terminal is used as a variable resistor, the unused terminal can be opened or shorted with W; such operation is called rheostat mode (see Figure 41). The resistance tolerance can range 20%.
A A A
03823-0-041
Figure 39. Power Supply Bypassing
The ground pin of the AD5251/AD5252 is used primarily as a digital ground reference. To minimize the digital ground bounce, the AD5251/AD5252 ground terminal should be joined remotely to the common ground (see Figure 39).
W B B
W B
W
DIGITAL POTENTIOMETER OPERATION
The structure of the RDAC is designed to emulate the performance of a mechanical potentiometer. The RDAC contains a string of resistor segments, with an array of analog switches acting as the wiper connection to the resistor array. The number of points is the resolution of the device. For example, the AD5251/AD5252 emulates 64 or 256 connection points with 64 or 256 equal resistance, RS, allowing it to provide better than 1.5%/0.4% settability resolution. Figure 40 provides an equivalent diagram of the connections between the three terminals that make up one channel of the RDAC. Switches SWA and SWB are always ON, while one of switches SW(0) to SW(2N-1) is ON one at a time, depending on the setting decoded from the data bit. Because the switches are nonideal, there is a 75 wiper resistance, RW. Wiper resistance is a function of supply voltage and temperature; lower supply voltages and higher temperatures result in higher wiper resistances. Consideration of wiper resistance dynamics is important in applications where accurate prediction of output resistance is required.
Figure 41. Rheostat Mode Configuration
The nominal resistance of the AD5251/AD5252 has 64 or 256 contact points accessed by the wiper terminal, plus the B terminal contact. The 6-or 8-bit data-word in the RDAC register is decoded to select one of the 64 or 256 settings. The wiper's first connection starts at the B terminal for Data 0x00. This B-terminal connection has a wiper contact resistance, RW, of 75 , regardless of the nominal resistance. The second connection (the AD5251 10 k part) is the first tap point where RWB = 231 (RWB = RAB/64 + RW = 156 + 75 ) for Data 0x01, and so on. Each LSB data value increase moves the wiper up the resistor ladder until the last tap point is reached at RWB = 9893 . See Figure 40 for a simplified diagram of the equivalent RDAC circuit. The general equation that determines the digitally programmed output resistance between W and B, is AD5251: RWB(D) = (D/64) x RAB + 75 AD5252: RWB(D) = (D/256) x RAB + 75 (1) (2)
Where D is the decimal equivalent data contained in the RDAC latch and RAB is the nominal end-to-end resistance.
Rev. 0 | Page 22 of 28
03823-0-040
DIGITAL CIRCUITRY OMITTED FOR CLARITY
SWB
AD5251/AD5252
100 RWA 75 RWB
PROGRAMMABLE POTENTIOMETER OPERATION
If all three terminals are used, the operation is called potentiometer mode and the most common configuration is the voltage divider operation (see Figure 43).
VI A
(%)
50
W
25
B
Figure 43. Potentiometer Mode Configuration
03823-0-042
0
0
If the wiper resistance is ignored, the transfer function is simply AD5251: VW = AD5252: VW =
D x V AB + V B 64 D x V AB + V B 256
16
32 D (Code in Decimal)
48
63
03823-0-043
VC
(5) (6)
Figure 42. AD5251 RWA(D) and RWB(D) vs. Decimal Code
Table 13. RWB vs. Codes; RAB = 10 k, A Terminal = Open
D (DEC) 63 32 1 0 RWB () 9918 5075 231 75 Output State Full scale Midscale 1 LSB Zero scale (wiper resistance)
A more accurate calculation, which includes the wiper resistance effect, yields
Note that in the zero-scale condition, a 75 finite wiper resistance is present. Care should be taken to limit the current conduction between W and B in this state to no more than 5 mA continuous for a total resistance of 1 k, or a 20 mA pulse, to avoid degradation or possible destruction of the internal switch contact. Similar to the mechanical potentiometer, the resistance of the RDAC between Wiper W and Terminal A also produces a digitally controlled complementary resistance, RWA. When these terminals are used, the B terminal can be opened. Setting the resistance value for RWA starts at a maximum value of resistance and decreases as the data loaded in the latch increases in value (see Figure 40). The general equation for this operation is AD5251: RWA(D) = [(64 - D)/64] x RAB + 75 AD5252: RWA(D) = [(256 - D)/256] x RAB + 75 (3) (4)
D R AB + RW N VA VW (D) = 2 R AB + 2RW
(7)
Where 2N is the number of steps. Unlike in rheostat mode operation where the tolerance is high, potentiometer mode operation yields an almost ratiometric function of D/2N with a relatively small error contributed by the RW terms. Therefore, the tolerance effect is almost cancelled. Similarly, the ratiometric adjustment also reduces the temperature coefficient effect to 50 ppm/C, except at low value codes where RW dominates. Potentiometer mode operations include other applications such as op amp input, feedback resistor networks, and other voltage scaling applications. The A, W, and B terminals can in fact be input or output terminals, provided |VA|, |VW|, and |VB| do not exceed VDD to VSS.
Table 14. RWA vs. Codes; AD5251, RAB=10 k, B Terminal Open
D (DEC) 63 32 1 0 RWA () 231 5075 9918 10075 Output State Full scale Midscale 1 LSB Zero scale
The typical distribution of RAB from channel-to-channel matches about 0.15% within a given device. On the other hand, device-to-device matching is process-lot dependent with 20% tolerance.
Rev. 0 | Page 23 of 28
AD5251/AD5252 APPLICATIONS
LCD PANEL VCOM ADJUSTMENT
Large LCD panels usually require an adjustable VCOM voltage centered around 6 V to 8 V with 1 V swing and small steps adjustment. This example represents common DAC applications where the window of adjustments is small and centered at any level. High voltage and high resolution DACs can be used but it is far more cost-effective to use low voltage digital potentiometers with level shifting, such as the AD5251 or AD5252, to achieve the objective. Assume a VCOM voltage requirement of 6 V 1 V with a 20 mV step adjustment, as shown in Figure 44. The AD5252 can be configured in voltage divider mode with an op amp gain. With 20% tolerance accounted for by the AD5252, this circuit can still be adjusted from 5 V to 7 V with an 8 mV/step in the worst case.
+14.4V
U1 RDAC1 10k V1 B +5V RSENSE 0.1k V+ V- U2 VO
AD5252
AD8628
V2
VREF
RDAC3 10k
Figure 45. Current-Sensing Amplifier.
ADJUSTABLE HIGH POWER LED DRIVER
Figure 46 shows a circuit that can drive three to four high power LEDs. The ADP1610 is an adjustable boost regulator that provides adequate headroom and current for the LEDs. Because its FB pin voltage is 1.2 V, the digital potentiometer AD5252 and the op amp form an average gain of 12 feedback networks that servo the sensing and feedback voltages. As a result, the voltage across RSET is regulated around 0.1 V, depending on the AD5252's setting. An adjustable LED current is I LED = V RSET R SET (9)
U1
R1 350k
1%
AD5252
+14.4V +5V VDD R2 10k B 20% V+ V- U2 6V 1V VCOM
R3 18.5k R5 1k R4 6k
C1 2.2p
03823-0-044
Figure 44. Apply 5 V Digital Potentiometer AD5251 in a 6 V 1 V Application.
RSET should be small to conserve power but large enough to limit the maximum LED current. R3 should also be used in parallel with the AD5252 to limit the LED current within an achievable range.
+5V C2 10F R4 13.5k U2 IN L1 10F D1 SW C3 10F VOUT
CURRENT-SENSING AMPLIFIER
The dual channel, synchronous update, and channel-to-channel resistance matching characteristics make the AD5251/AD5252 suitable for current sensing applications, such as LED brightness control. In the circuit shown in Figure 45, when RDAC1 and RDAC3 are programmed to the same settings, it can be shown that
D (V2 - V1 ) + VREF Vo = N 2 -D
ADP1610
PWM /SD FB COMP
03823-0-045
B
D1 RO 100k CC 390pF SS RT GND D2 CSS 10nF D3 C8 +5V 0.1F U3 V+
(8)
As a result, the current through a sense resistor connected between V1 and V2 can be known. The programmability of this circuit makes it adaptable to systems that require different sensitivities. If the op amp has very low offset and low bias current, the major source of error comes from the digital potentiometer channel-to-channel resistance mismatch, which is typically 0.15%. The circuit accuracy is about 9 bits, which is adequate for LED control and other general purpose applications.
AD8591
V- U1 U1 W B R2 1.1k 10k A R1 100
03823-0-046
RSET 0.25k
AD5252
R3 200
Figure 46. High Power Adjustable LED Driver
Rev. 0 | Page 24 of 28
AD5251/AD5252 OUTLINE DIMENSIONS
5.10 5.00 4.90
14
8
4.50 4.40 4.30
1 7
6.40 BSC
PIN 1 1.05 1.00 0.80 0.65 BSC 1.20 MAX 0.15 0.05 0.30 0.19 0.20 0.09 8 0 0.75 0.60 0.45
SEATING COPLANARITY PLANE 0.10
COMPLIANT TO JEDEC STANDARDS MO-153AB-1
Figure 47. 14-Lead Thin Shrink Small Outline Package [TSSOP] (RU-14) Dimensions shown in millimeters
ORDERING GUIDE
Model AD5251BRU1 AD5251BRU1-RL7 AD5251BRU10 AD5251BRU10-RL7 AD5251BRU50 AD5251BRU50-RL7 AD5251BRU100 AD5251BRU100-RL7 AD5251EVAL AD5252BRU1 AD5252BRU1-RL7 AD5252BRU10 AD5252BRU10-RL7 AD5252BRU50 AD5252BRU50-RL7 AD5252BRU100 AD5252BRU100-RL7 AD5252EVAL Step 64 64 64 64 64 64 64 64 64 256 256 256 256 256 256 256 256 256 RAB (k) 1 1 10 10 50 50 100 100 10 1 1 10 10 50 50 100 100 10 Temperature Range (C) -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 Package Description TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP Evaluation Board TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP Evaluation Board Package Option RU-14 RU-14 RU-14 RU-14 RU-14 RU-14 RU-14 RU-14 RU-14 RU-14 RU-14 RU-14 RU-14 RU-14 RU-14 RU-14 Full Container Quantity 96 1,000 96 1,000 96 1,000 96 1,000 1 96 1,000 96 1,000 96 1,000 96 1,000 1 Branding1 B1 B1 B10 B10 B50 B50 B100 B100 B1 B1 B10 B10 B50 B50 B100 B100
1
In the package marking, Line 1 shows the part number; Line 2 shows the branding information, such that B1 = 1 k, B10 = 10 k, B50 = 50 k, and B100 = 100 k; Line 3 shows the date code in YYWW.
Rev.0 | Page 25 of 28
AD5251/AD5252 NOTES
Rev. 0 | Page 26 of 28
AD5251/AD5252 NOTES
Rev. 0 | Page 27 of 28
AD5251/AD5252 NOTES
Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
(c) 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D03823-0-6/04(0)
Rev. 0 | Page 28 of 28

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